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| lt8582 1 8582f typical application features description dual 3a boost/inverting/sepic dc/dc converter with fault protection the lt ? 8582 is a dual independent channel pwm dc/dc converter with a power good pin and built-in fault protection to help guard against input overvoltage and overtempera- ture conditions. each channel consists of a 42v master switch and a 42v slave switch that can be tied together for a total current limit of 3a. the lt8582 is ideal for many local power supply designs. each channel can be easily configured in boost, sepic, inverting, or flyback configurations. together, the two chan- nels can produce a 12v and a C12v output with 14.4w of combined output power from a 5v input. in addition, the lt8582s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are more efficient and require fewer components than traditional circuits. the lt8582 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. additional features such as output short protection, frequency foldback and soft-start are integrated. the lt8582 is available in a 24-pin 7mm 4mm dfn package. 1.5mhz, 5v to 12v efficiency and power loss (load between 12v and C12v outputs) applications n local power supply n vacuum fluorescent display (vfd) bias supplies n tft-lcd bias supplies n automotive engine control unit (ecu) power l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7579816. n dual 42v, 3a combined power switch n master/slave (1.7a/1.3a) switch design n wide input range: 2.5v to 22v operating, 40v maximum transient n power good pin for event based sequencing n switching frequency up to 2.5mhz n each channel easily configurable as a boost, sepic, inverting or flyback converter n low v cesat switch: 270mv at 2.75a (typical) n can be synchronized to an external clock n output short-circuit protection n high gain shdn pin accepts slowly varying input signals n 24-pin 7mm 4mm dfn package load current (a) 0 20 efficiency (%) power loss (w) 30 8070 60 50 90 0.2 0.3 0.6 8582 ta01b 40 0.1 0.4 0.5 100 0 0.4 2.42.0 1.6 1.2 2.8 0.8 3.2 swb2 swa2 swb1 swa1 lt8582 8582 ta01a pg1sync1 clkout1 clkout2 215k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 12v550ma v out2 C12v550ma 4.7f 2.2f v in 5v 0.1f 6.04k 0.1f 53.6k 53.6k 4.7nf 47pf 47pf 14.7k 6.49k 100k 100k 143k 215k 4.7h s 4.7h s 2.2nf 10f 10f 130k 4.7f 10f 4.7h downloaded from: http:///
lt8582 2 8582f pin configuration absolute maximum ratings v in1 voltage ............................................... C0.3v to 40v swa1/swb1 voltage .................................. C0.4v to 42v rt1 voltage ................................................. C0.3v to 5v ss1 voltage .............................................. C0.3v to 2.5v fbx1 voltage ................................................ C0.3v to 5v v c1 voltage .................................................. C0.3v to 2v shdn1 voltage .........................................................40v shdn1 current ...................................................... C1ma sync1 voltage .......................................... C0.3v to 5.5v gate1 voltage ........................................... C0.3v to 60v pg1 voltage ............................................... C0.3v to 40v pg1 current ........................................................0.5ma clkout1 ........................................................... (note 5) operating junction temperature range lt8582e ............................................ C40c to 125c lt8582i ............................................. C40c to 125c storage temperature range .................. C65c to 150c note: absolute maximum ratings are shown for channel 1 only. channel 2 ratings are identical. top view 25 gnd dkd package 24-lead (7mm 4mm) plastic dfn swa1 v in1 pg1 gate1 v c1 fbx1fbx2 v c2 gate2 pg2 v in2 swa2 swb1 clkout1 shdn1 rt1 ss1 sync1 sync2 ss2 rt2 shdn2 clkout2 swb2 12 11 10 13 14 15 16 17 18 19 20 21 22 23 24 9 8 7 6 5 4 3 2 1 t jmax = 125c, ja = 34c/w, jc = 7c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8582edkd#pbf lt8582edkd#trpbf 8582 24-pin (7mm 4mm) plastic dfn C40c to 125c lt8582idkd#pbf lt8582idkd#trpbf 8582 24-pin (7mm 4mm) plastic dfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (note 1) downloaded from: http:/// lt8582 3 8582f electrical characteristics parameter conditions min typ max units minimum input voltage v in l 2.3 2.5 v v in overvoltage lockout 22.2 24.5 27 v positive feedback voltage l 1.185 1.204 1.220 v negative feedback voltage l 2 7 16 mv positive fbx pin bias current v fbx = positive feedback voltage, current into pin l 81 83.3 85 a negative fbx pin bias current v fbx = negative feedback voltage, current out of pin l 81 83.3 85.5 a error amp transconductance i = 10a 280 mhos error amp voltage gain 80 v/v quiescent current v shdn = 2.5v, not switching 2.1 2.5 ma quiescent current in shutdown v shdn = 0 0 1 a reference line regulation 2.5v v in 20v 0.01 0.05 %/v switching frequency, f osc r t = 31.6k r t = 407k ll 2.125 170 2.5 200 2.875 230 mhz khz switching frequency in foldback compared to normal f osc 1/6 ratio switching frequency range free-running or synchronizing l 200 2500 khz sync high level for sync l 1.3 v sync low level for sync l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended min sync ratio f sync /f osc 3/4 ratio minimum off-time 45 ns minimum on-time 55 ns swa current limit minimum duty cycle maximum duty cycle ll 1.81.3 2.41.8 3 2.5 aa swa fault current limit minimum duty cycle maximum duty cycle ll 2.21.6 2.82.3 3.53.0 aa sw current sharing, i swb /i swa swa and swb tied together 0.79 a/a swa + swb current limit minimum duty cycle, i swb /i swa = 0.79 maximum duty cycle, i swb /i swa = 0.79 ll 3.32.3 4.34.1 5.44.5 aa swa + swb fault current limit minimum duty cycle, i swb /i swa = 0.79 maximum duty cycle, i swb /i swa = 0.79 ll 4 2.8 54 6.35.4 aa switch v cesat i swa + i swb = 2.75a 270 mv swa leakage current v swa = 5v, v shdn = 0 0.01 1 a swb leakage current v swb = 5v, v shdn = 0 0.01 1 a ss charge current v ss = 30mv, current flows out of ss pin l 5.7 8.8 11.7 a ss discharge current part in fault, v ss = 2.1v, current flows into ss pin l 5.7 8.8 11.7 a ss high detection voltage part in fault l 1.65 1.84 2 v ss low detection voltage part exiting fault l 15 55 100 mv shdn minimum input voltage high active mode, shdn rising active mode, shdn falling ll 1.261.21 1.311.27 1.4 1.35 vv shdn input voltage low shutdown mode l 0.3 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , unless otherwise noted (note 2). specifications are identical for both channels unless noted otherwise. downloaded from: http:/// lt8582 4 8582f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8582e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the lt8582i is guaranteed over the full C40c to 125c operating junction temperature range. parameter conditions min typ max units shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 10.1 45 12.1 0 65 14.1 0.1 aa a clkout output voltage high 1ma out of clkout pin 1.9 2.1 2.3 v clkout output voltage low 1ma into clkout pin 30 200 mv clkout1 duty cycle all t j 50 % clkout2 duty cycle t j = C40c t j = 25c t j = 125c 22.5 4272 %% % clkout rise time c clkout = 120pf 25 ns clkout fall time c clkout = 120pf 15 ns gate pull-down current v gate = 3v v gate = 20v ll 0.80.8 11 1.21.2 mama gate leakage current v gate = 50v, gate off 0.01 1 a pg threshold for positive feedback voltage v fbx rising 1.09 1.15 1.20 v pg threshold for negative feedback voltage v fbx falling 20 65 120 mv pg hysteresis for feedback voltage 4m v pg output voltage low 100a into pg pin, v fbx = 1v l 70 150 mv pg leakage current v pg = 40v, v fbx = 1.204v 0.01 1 a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , unless otherwise noted (note 2). specifications are identical for both channels unless noted otherwise. note 3: current limit guaranteed by design and/or correlation to static test. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation over the specified maximum operating junction temperature may impair device reliability. note 5: do not apply a positive or negative voltage or current source to clkout, otherwise permanent damage may occur. downloaded from: http:/// lt8582 5 8582f typical performance characteristics switch current limit at minimum duty cycle clkout duty cycle oscillator frequency switching frequency during soft-start gate pin current (v ss = 2.1v) switch current limit vs duty cycle switch saturation voltage switch current sharing t a = 25c, unless otherwise noted. swa current (a) 0 0 i swb /i swa (a/a) 0.40.3 0.2 0.1 0.6 0.80.7 0.9 1 1.5 3.5 8582 g03 0.5 0.5 2 2.5 3 1.0 temperature (c) C50 0 swa + swb current (a) 21 3 4 0 25 150 8582 g04 C25 50 75 100 125 5 temperature (c) C50 0 clkout duty cycle (%) 4020 60 80 0 150 8582 g06 C25 25 50 75 100 125 100 channel 1 channel 2 gate pin voltage (v) 0 gate pin current (a) 60 8582 g09 10 20 30 40 50 11001000 900800 700 600 500 400 300 200 100 0 t a = C40c t a = 25c t a = 125c ss voltage (v) 0 0 swa + swb current (a) 21 3 4 0.4 1.2 8582 g05 0.2 0.6 0.8 1 5 commanded current limit vs ss voltage temperature (c) C50 0.2 frequency (mhz) 0.60.4 0.0 0.8 1.0 1.2 1.4 1.6 2.42.2 2.0 1.8 0 150 8582 g07 C25 25 50 75 100 125 2.82.6 3.0 r t = 31.6k r t = 402k duty cycle (%) 10 0 swa + swb current (a) 1 3 4 40 50 90 8582 g01 2 20 30 60 70 80 5 swa + swb current (a) 0 0 saturation voltage (mv) 50 150 250200 300 1 1.5 3.5 8582 g02 100 0.5 2 2.5 3 350 v sw1 = v sw2 fbx voltage (v) 0 normalized oscillator frequency (f sw /f nom ) 1/41/5 1/3 1/2 1.2 8582 g08 0.2 0.4 0.6 0.8 1 1 invertingconfigurations noninverting configurations downloaded from: http:/// lt8582 6 8582f typical performance characteristics shdn pin current shdn pin current internal uvlo clkout rise and fall times at 1mhz v in overvoltage lockout pg threshold gate pin current (v gate = 5v) active/lockout threshold t a = 25c, unless otherwise noted. ss voltage (v) 0 gate pin current (a) 1.5 8582 g10 0.25 0.5 0.75 1 1.25 1000 900800 700 600 500 400 300 200 100 0 shdn voltage (v) 0 shdn pin current (a) 2 8582 g13 0.25 0.50 0.75 1 1.75 1.25 1.50 3025 20 15 10 50 t a = C40c t a = 25c t a = 125c shdn voltage (v) 0 shdn pin current (a) 40 8582 g14 5 10 15 20 35 25 30 300250 200 150 100 50 0 t a = C40c t a = 25c t a = 125c temperature (c) C50 v in voltage (v) 150 8582 g15 C25 0 25 50 125 75 100 2.502.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 clkout capacitive load (pf) clkout transition time (ns) 150 8582 g16 0 25 50 125 75 100 4035 30 25 20 15 10 50 rise time fall time temperature (c) v in voltage (v) 150 8582 g17 C50 C25 0 100 125 50 25 75 2827 26 25 24 23 22 20 19 2118 positive feedback voltage temperature (c) C50 fbx voltage (v) 150 8582 g11 C25 0 25 50 75 100 125 1.2201.215 1.210 1.205 1.200 1.195 1.190 temperature (c) fbx voltage (v) 150 8582 g18 C50 C25 0 100 125 50 25 75 1.501.25 1.00 0.75 0.25 0.50 0 temperature (c) C50 shdn voltage (v) 150 8582 g12 C25 0 25 50 75 100 125 1.401.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 shdn rising shdn falling downloaded from: http:/// lt8582 7 8582f pin functions fbx1, fbx2 (pin 6/pin 7): positive and negative feedback pins. for an inverting or noninverting output converter, tie a resistor from the fbx pin to v out according to the following equations: r ; noninverting converter fbx = v out C 1.204v 83.3a ?? ? ?? r fbx = | | v out | | + 7mv 83.3a ; inverting converter ?? ? ?? vc1, vc2 (pin 5/pin 8): error amplifier output pins. tie external compensation network to these pins. gate1, gate2 (pin 4/pin 9): pmos gate drive pins. the gate pin is a pull-down current source and can be used to drive the gate of an external pmos transistor for output short-circuit protection or output disconnect. the gate pin current increases linearly with the ss pin voltage, with a maximum pull-down current of 1ma at ss voltages exceeding 550mv. note that if the ss voltage is greater than 550mv and the gate pin voltage is less than 2v, the gate pin looks like a 2k impedance to ground. see the appendix for more information. pg1, pg2 (pin 3/pin 10): power good indication pins. this active high pin indicates that the fbx pin voltage for the corresponding channel is within 4% of its regulation voltage (v fbx > 1.15v for noninverting outputs or v fbx < 65mv for inverting outputs). for most applications, a 4% change in v fbx corresponds to an 8% change in v out . this open drain output requires a pull-up resistor to indicate power good. also, the status is valid only when shdn > 1.31v and v in > 2.3v. vin1, vin2 (pin 2/pin 11): input supply pins. must be locally bypassed. swa1, swa2 (pin 1/pin 12): master switch pins. this is the collector of the internal master npn power switch for each channel. swa is designed to handle a peak collector current of 1.7a (minimum). minimize the metal trace area connected to this pin to minimize emi. swb1, swb2 (pin 24/pin 13): slave switch pins. this is the collector of the internal slave npn power switch for each channel. swb is designed to handle a peak collector current of 1.3a (minimum). minimize the metal trace area connected to this pin to minimize emi. clkout1, clkout2 (pin 23/pin 14): clock output pins. use these pins to synchronize one or more other ics to either channel of the lt8582. can also be used to syn- chronize channel 1 or channel 2 of the lt8582 with the other channel of the lt8582. this pin oscillates at the same frequency as the internal oscillator of the part or, if active, the sync pin. the clkout pin signal on ch1 is 180 out of phase with the internal oscillator or sync pin and the duty cycle is fixed at ~50%. the clkout pin signal on ch2 is in phase with the internal oscillator or sync pin and the duty cycle varies linearly with the parts junction temperature. note that clkout of either channel is only meant to drive capacitive loads up to 120pf. shdn1 , shdn2 (pin 22/pin 15): shutdown pins. in conjunction with the uvlo (undervoltage lockout) circuit, these pins are used to enable/disable the channel and restart the soft-start sequence. drive below 0.3v to dis- able the channel with very low quiescent current. drive above 1.31v (typical) to activate the channel and restart the soft-start sequence. do not float these pins. rt1, rt2 (pin 21/pin 16): timing resistor pins. adjusts the switching frequency of the corresponding channel. place a resistor from these pins to ground to set the frequency to a fixed free running level. do not float these pins. ss1, ss2 (pin 20/pin 17): soft-start pins. place a soft- start capacitor here. upon start-up, the ss pins will be charged by a (nominally) 250k resistor to ~2.1v. during a fault, the ss pin for the corresponding channel will be slowly charged up and discharged as part of a timeout sequence (see the state diagram for more information). sync1, sync2 (pin 19/pin 18): use to synchronize the switching frequency of a channel to an outside clock. the high voltage level of the clock must exceed 1.3v and the low level must be less than 0.4v. drive these pins to less than 0.4v to revert to the internal free running clock for the corresponding channel. see the applications information section for more information. gnd (exposed pad pin 25): ground. exposed pad must be soldered directly to local ground plane. (ch1/ch2) downloaded from: http:/// lt8582 8 8582f block diagram figure 1. block diagram C + 250k 1.84v 1.31v 50k v in1 2.1v vc1 55mv driverdisable i swa1 comparator die temp165c v in1 22.2v(min) 2a (min) gnd swa1 swb1 8582 bd start-up and fault logic soft-start rq s sr1 driver C + C + C + C + C + C + C + fbx1 1.15v65mv fbx1 C + C + 7 # & t t d ~ 30ns C + 1.204v reference frequency foldback adjustable oscillator 14.5k a1a2 C + a3 C + a4 sync1 rt1 ss1 clkout** v c1 14.5k n uvlo sync block ramp generator shdn1 ss1 c ss 28m q2 q1 r s 22m r t r c c c v out v in r gate fbx1 r fbx pg1 gate1 1ma m 1 r pg l1 d1 optional c in c out1 c out2 **block diagram for ch1 is shown. block diagram for ch2 is identical, except clkout signal for ch1 is 180 out of phase with the internal oscillator and has a fixed 50% duty cycle and clkout signal for ch2 is in phase with the internal oscillator and its duty cycle varies linearly with the parts junction temperature. downloaded from: http:/// lt8582 9 8582f state diagram figure 2. state diagram 8582 sd t " - - 4 8 * 5 $ ) & 4 % * 4 " # - & % t * ( " 5 & 0 ' ' t ' " 6 - 5 t $ - & " 3 & % chip off t 4 4 1 * / 1 6 - - & % - 0 8 initialize t * ( " 5 & & / " # - & % t 4 4 1 * / $ ) " 3 ( & 4 6 1 t 4 8 * 5 $ ) & 3 & / " # - & % soft-start t 2 " / % 2 4 8 * 5 $ ) & 4 ' 0 3 $ & % 0 / & 7 & 3 : $ : $ - & ' 0 3 " 5 - & " 4 5 . * / * . 6 . 0 / 5 * . & t * ( " 5 & ' 6 - - : " $ 5 * 7 " 5 & % 8 ) & / 4 4 n 7 t 1 ( 1 * / 1 6 - - & % - 0 8 # : - 5 sample mode t / 0 3 . " - 0 1 & 3 " 5 * 0 / t $ - , 0 6 5 & / " # - & % 8 ) & / 4 4 7 t 1 ( 1 * / 1 6 - - % 0 8 / 3 & - & " 4 & % # : - 5 normal mode t 4 4 $ ) " 3 ( & 6 1 t * ( " 5 & 0 ' ' t 4 8 * 5 $ ) & 3 % * 4 " # - & % t $ - , 0 6 5 % * 4 " # - & % shdn1 7 0 3 7 * / 7 shdn1 7 " / % 7 * / 7 ' # 9 7 / 0 / * / 7 & 3 5 * / ( 0 3 ' # 9 n 7 * / 7 & 3 5 * / ( * ' ] 7 0 6 5 ] % 3 0 1 4 $ " 6 4 * / ( ' # 9 7 / 0 / * / 7 & 3 5 * / ( 0 3 ' # 9 n 7 * / 7 & 3 5 * / ( 4 5 " 5 & % * " ( 3 " . ' 0 3 $ ) * 4 4 ) 0 8 / 4 5 " 5 & % * " ( 3 " . ' 0 3 $ ) * 4 * % & / 5 * $ " - " / % * / % & 1 & / % & / 5 ' 3 0 . $ ) ' " 6 - 5 4 4 1 * / n 7 4 4 1 * / 7 " / % / 0 ' " 6 - 5 $ 0 / % * 5 * 0 / 4 4 5 * - - % & 5 & $ 5 & % 4 4 n 7 fault detected t 4 4 1 * / 4 - 0 8 - : % * 4 $ ) " 3 ( & 4 post fault delay ' " 6 - 5 ' " 6 - 5 ' " 6 - 5 ' " 6 - 5 0 7 & 3 7 0 - 5 " ( & 1 3 0 5 & $ 5 * 0 / 0 / 7 * / 7 * / 7 . * / 0 7 & 3 5 & . 1 & 3 " 5 6 3 & 5 + 6 / $ 5 * 0 / ? $ 0 7 & 3 $ 6 3 3 & / 5 0 / 4 8 " * 4 8 " " . * / % 6 5 : $ : $ - & % & 1 & / % & / 5 downloaded from: http:/// lt8582 10 8582f operation operation C overview the lt8582 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. each channels undervoltage lockout (uvlo) function, together with soft-start and frequency foldback, offer a controlled means of starting up. fault features are incorporated into each channel of the lt8582 to facilitate the detection of output shorts, overvoltage and overtemperature condi- tions. please refer to the block diagram (figure 1) and the state diagram (figure 2) for the following description of the parts operation. operation C start-up several functions are provided to enable a very clean start-up of both channels of the lt8582. precise turn-on voltage the shdn pin on each channel is compared to an internal voltage reference to give a precise turn on voltage level. tak- ing each shdn pin above 1.31v enables the corresponding channel. taking each shdn pin below 300mv shuts down the channel, resulting in extremely low quiescent current for that channel. the shdn pin has 35mv of hysteresis to protect against glitches and slow ramping. configurable undervoltage lockout (uvlo) the shdn pin can also be used to create a configurable uvlo for each channel. this function sets the turn on/ off of each of lt8582s channels at a desired voltage (vin uvlo ). figure 3 shows how a resistor divider (or a single resistor) from v in to the shdn pin can be used to program vin uvlo . r uvlo2 is optional. if left out, set it to infinite in the equation below. for increased accuracy, set r uvlo2 10k. pick r uvlo1 as follows: vin uvlo r uvlo1 = C1.31v 1.31v r uvlo2 ?? ? ?? + 12.3a internal undervoltage lockout (uvlo) regardless of where external circuitry sets vin uvlo , the lt8582 also has internal uvlo circuitry that disables the chip when v in < 2.3v (typical). soft-start of switch current the soft-start circuitry provides for a gradual ramp-up of the switch current in each channel (refer to commanded current limit vs ss voltage in typical performance characteristics). when the channel is taken out of shut- down, the external ss capacitor is first discharged. this resets the state of the logic circuits in the channel. then an integrated 250k resistor pulls the channels ss pin to ~1.84v. the ramp rate of the ss pin voltage is set by this 250k resistor and the external capacitor connected to this pin. once ss gets to ~1.84v, the clkout pin is enabled and an internal regulator pulls the pin up quickly to ~2.1v. typical values for the external soft-start capacitor range from 100nf to 1f. soft-start of external pmos (if used) the soft-start circuitry also gradually ramps up the gate pin pull-down current for the corresponding channel. this allows an external pmos to slowly turn on (m1 in block diagram). the gate pin current increases linearly with ss voltage, with a maximum current of 1ma when the ss voltage gets above 550mv. note that if the gate pin voltage is less than 2v for ss voltages exceeding 550mv, then the gate pin impedance to ground is 2k. the soft turn on of the external pmos helps limit inrush current at start up, making hot plugs of lt8582s feasible. figure 3. configurable uvlo 1.31v gnd active/ lockout shdn 8582 f03 v in v in r uvlo2 (optional) r uvlo1 C + 12.3a at 1.31v downloaded from: http:/// lt8582 11 8582f operation sample mode sample mode is the mechanism used by the lt8582 to aid in the detection of output shorts. it refers to a state of the lt8582 where the master and slave power switches (q1 and q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to sample the inductor current. if the sampled current through q1 exceeds the master switch fault current limit of 2a (minimum), the lt8582 triggers an overcurrent fault internally for that channel (see op- eration C fault section for details). sample mode exists when fbx for that channel is out of regulation by more than 4% (65mv < fbx < 1.15v). during this mode, pg will be pulled low. frequency foldback the frequency foldback circuit reduces the switching frequency for that channel when 144mv < fbx < 1.03v (typical). this feature lowers the minimum duty cycle that the channel can achieve, thus allowing better control of the inductor current during start-up. when the fbx volt- age is pulled outside of the above mentioned range, the switching frequency for that channel returns to normal. note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target v out , v in , switching frequency, etc. operation C regulation the following description of the lt8582s operation as- sumes that the fbx voltage is close enough to its regulation target so that the part is not in sample mode. also, this description applies equally to both channels independently of each other. use the block diagram as a reference when stepping through the following description of the lt8582 operating in regulation. at the start of each oscillator cycle, the sr latch (sr1) is set, which turns on the power switches q1 and q2. the collector current through the master switch, q1, is ~1.3 times the collector current through the slave switch, q2, when the collectors of the two switches are tied together. q1s emitter current flows through a current sense resis- tor (r s ) generating a voltage proportional to the switch current. this voltage (amplified by a4) is added to a sta-bilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a3. when the voltage on the positive input of a3 exceeds the voltage on the nega- tive input, the sr latch is reset, turning off the master and slave power switches. the voltage on the negative input of a3 (v c pin) is set by a1 (or a2), which is simply an amplified difference between the fbx pin voltage and the reference voltage (1.204v if the lt8582 is configured as a noninverting converter, or 7mv if configured as an invert- ing converter). in this manner, the error amplifier sets the correct peak current level to maintain output regulation. as long as the channel is not in fault and the ss pin ex- ceeds 1.84v, the lt8582 drives the clkout pin for that channel at the frequency set by the rt pin or the sync pin. the clkout pin can synchronize other ics, including additional lt8582s or the other channel of an lt8582, up to 120pf load on clkout. for channel 1, clkout1 has a fixed duty cycle and is 180 out of phase with the internal clock. for channel 2, clkout2s duty cycle varies linearly with channel 2s junction temperature and may be used as a temperature monitor. operation C fault each of the following events can trigger a fault in the lt8582: 1. sw overcurrent: a. i swa > 2a (minimum) b. (i swa + i swb ) > 3.5a (minimum) 2. v in voltage > 22.2v (minimum) 3. die temperature > 165c downloaded from: http:/// lt8582 12 8582f operation refer to the state diagram (figure 2) for the following description of the lt8582s operation during a fault event. when a fault is detected on a channel, the lt8582 disables the clkout pin for that channel, turns off the power switches for that channel and the gate pin for that channel becomes high impedance. the external pmos, m1, is turned off by the external r gate resistor (see block diagram). with the external pmos turned off, the power path from v in to v out is opened, protecting power path components. also, as soon as the feedback voltage falls inside the range 65mv < fbx < 1.15v, pg pulls low. refer to figure 4 for the case of an output short. at the beginning of a fault event, a timeout sequence com- mences where the ss pin for that channel is charged up to 1.84v (the ss pin will continue charging up to ~2.1v and be held there in the case of a fault event that still exists) and then discharged to 55mv. this timeout period relieves the chip, the pmos and other power path components from electrical and thermal stress for a minimum amount of time set by the voltage ramp rate on the ss pin. figure 4. output short-circuit protection of the lt8582 operation C current limit the current limit operates independently of the fault current limit. the current limit sets a maximum switch current. this switch current limit is duty cycle dependent, but for most applications will be around 3a minimum (see the electrical characteristics). once this limit is reached, the switch duty cycle decreases, reducing the magnitude of the output voltage. if, despite the reduced duty cycle the switch current reaches the fault current limit, the part will behave as described in the operation C fault section. clkout 5v/div v out1 5v/div i l1 5a/div gate 5v/div 20s/div 8582 f04 downloaded from: http:/// lt8582 13 8582f boost converter component selection table 1. boost converter design equations parameters/equations step 1: inputs choose v in , v out and f osc to calculate equations below. step 2: dc dc ? v out Cv in + 0.5v v out + 0.5v C 0.3v step 3: l1 l typ = (v in C 0.3) ? dc f osc ?1a (1) l min = (v in C0.3v)?(2?dcC1) 1.7a ? f osc ?(1Cdc) (2) l max = (v in C0.3v)?dc f osc ?0.18a (3) ? solve equations 1, 2 and 3 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is l max step 4: i ripple i ripple = (v in C 0.3v) ? dc f osc ?l 1 step 5: i out i out = 3a C i ripple 2 ?? ? ?? ? ? (1 C dc) step 6: d1 v r v out ; i avg i out step 7: c out c out1 " c out2 v i out t dc f osc (0.01 t v out C0.5 t i out t r dson_pmos ) ? if pmos is not used, then use just one capacitor where c out = c out1 + c out2 step 8: c in c in v c vin c pwr v 3a t dc 50 t f osc t 0.005 t v in 8 t f osc t 0.005 t v in i ripple step 9: r fbx r fbx = v out C 1.204v 83.3a ?? ? ?? step 10: r t r t = 81.6 f osc C1; f osc in mhz and r t in k step 11: pmos only needed for input or output disconnect. see pmos selection in the appendix for information on sizing the pmos and the biasing resistor, r gate and picking appropriate uvlo components. note 1: above equations use numbers good for many applications but for more exact results use the equations from the appendix with numbers from the electrical characteristics. note 2: the final values for c out1 , c out2 and c in may deviate from the above equations in order to obtain desired load transient performance. applications information figure 5. boost converter C the component values given are typical values for a 1.5mhz, 5v to 12v boost each channel of the lt8582 can be configured as a boost converter as in figure 5. this topology allows for positive output voltages that are higher than the input voltage. an external pmos (optional) driven by the gate pin of the lt8582 can achieve input or output disconnect during a fault event, shdn < 1.31v, or v in < 2.3v. figure 5 shows the configuration for output disconnect. a single feedback resistor sets the output voltage. for output voltages higher than 40v, see the charge pump topology in the charge pump aided regulators section. table 1 is a step-by-step set of equations to calculate component values for the lt8582 when operating as a boost converter. input parameters are input and output voltage and switching frequency (v in , v out and f osc re- spectively). refer to the appendix for further information on the design equations presented in table 1. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current r dson_pmos = r dson of external output pmos (set to 0 if not using pmos) ss gnd sync swb d1 30v, 2a m1 swa lt8582 chx 8582 f05 pgrt 215k v in shdn clkout v c fbx gate v out 12v0.8a v in 5v 100k r t 53.6k c out1 10f 6.04k 6.49k l1 4.7h optional r fbx 130k c in 4.7f 0.1f 4.7nf 47pf c out2 10f downloaded from: http:/// lt8582 14 8582f applications information sepic converter component selection C coupled or uncoupled inductors each channel of the lt8582 can also be configured as a sepic as shown in figure 6. this topology allows for posi- tive output voltages that are lower, equal, or higher than the input voltage. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output due to capacitor c1. therefore the external pmos is not required. table 2 is a step-by-step set of equations to calculate component values for the lt8582 when operating as a sepic converter. input parameters are input and output voltage and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 2. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current figure 6. sepic converter C the component values given are typical values for a 700khz, 3v - 19v to 5v sepic topology using coupled inductors table 2. sepic design equations parameters/equations step 1: inputs choose v in , v out and f osc to calculate equations below. step 2: dc dc ? v out + 0.5v v in + v out + 0.5v C 0.3v step 3: l l typ = (v in C 0.3v) ? dc f osc ?1a (1) l min = (v in C0.3v)?(2?dcC1) 1.7a ? f osc ?(1Cdc) (2) l max = (v in C0.3v)?dc f osc ? 0.18a (3) ? solve equations 1, 2 and 3 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is l max ? l = l1 = l2 for coupled inductors. ? l = l1||l2 for uncoupled inductors. step 4: i ripple i ripple = (v in C 0.3v) ? dc f osc ?l step 5: i out i out = 3a C i ripple 2 ?? ? ?? ? ? (1 C dc) step 6: d1 v r v in + v out ; i avg i out step 7: c1 c1 1f; v rating v in step 8: c out c out i out ?dc f osc ? 0.005 ? v out step 9: c in c in c vin + c pwr 3a ? dc 50 ? f o sc ? 0.005 ? v in + i ripple 8?f o sc ? 0.005 ? v in step 10: r fbx r fbx = v out C 1.204v 83.3a ?? ? ?? step 11: r t r t = 81.6 f osc C1; f osc in mhz, r t in k note 1: above equations use numbers good for many applications but for more exact results use the equations from the appendix with numbers from the electrical characteristics. note 2: the final values for c out , and c in may deviate from the above equations in order to obtain desired load transient performance. ss gnd sync swb c1 2.2f swa lt8582 chx 8582 f06 pgrt v in shdn clkout v c fbx gate v out 5v1a(v in >12v) v in 3v to 19v 100k r t 107k 14.7k l1 6.8h d1 40v, 2a r fbx 45.3k c in 10f 0.1f 1.5nf 47pf c out 22f2 s s l26.8h downloaded from: http:/// lt8582 15 8582f applications information dual inductor inverting converter component selection C coupled or uncoupled inductors figure 7. dual inductor inverting converter C the component values given are typical values for a 1.5mhz, 5v to C12v inverting topology using coupled inductors table 3. dual inductor inverting design equations parameters/equations step 1: inputs choose v in , v out and f osc to calculate equations below. step 2: dc dc ? |v out | + 0.5v v in + |v out | + 0.5v C 0.3v step 3: l l typ = (v in C 0.3v) ? dc f osc ?1a (1) l min = (v in C0.3v)?(2?dcC1) 1.7a ? f osc ?(1Cdc) (2) l max = (v in C 0.3v) ?dc f osc ? 0.18a (3) ? solve equations 1, 2 and 3 for a range of l values ? the minimum of the l value range is the higher of l typ and l min ? the maximum of the l value range is l max ? l = l1 = l2 for coupled inductors. ? l = l1||l2 for uncoupled inductors. step 4: i ripple i ripple = (v in C 0.3v) ? dc f osc ?l step 5: i out i out = 3a C i ripple 2 ?? ? ?? ? ? (1 C dc) step 6: d1 v r > v in + |v out |; i avg > i out step 7: c1 c1 1f; v rating v in + |v out | step 8: c out c out i ripple 8 t f osc t 0.005 t |v out | step 9: c in c in c vin + c pwr 3a ?dc 50 ? f o sc ? 0.005 ? v in + i ripple 8?f o sc ? 0.005 ? v in step 10: r fbx r fbx = |v out | + 7mv 83.3a step 11: r t r t = 81.6 f osc C1; f osc in mhz, r t in k note 1: above equations use numbers good for many applications but for more exact results use the equations from the appendix with numbers from the electrical characteristics. note 2: the final values for c out , and c in may deviate from the above equations in order to obtain desired load transient performance. due to its unique fbx pin, each channel of the lt8582 can work in a dual inductor inverting configuration as shown in figure 7. changing the connections of l2 and the schottky diode in the sepic topology results in generating negative output voltages. this configuration results in very low output voltage ripple due to inductor l2 in series with the output. output disconnect is inherently built into this topology because of capacitor c1. table 3 is a step-by-step set of equations to calculate component values for the lt8582 when operating as a dual inductor inverting converter. input parameters are input and output voltage and switching frequency (v in , v out and f osc respectively). refer to the appendix for further information on the design equations presented in table 3. variable definitions: v in = input voltage v out = output voltage dc = power switch duty cycle f osc = switching frequency i out = maximum output current i ripple = inductor ripple current ss gnd sync swb c1 2.2f swa lt8582 chx 8582 f07 pgrt v in shdn clkout v c fbx gate v out C12v550ma v in 5v 100k r t 53.6k 14.7k l1 4.7h l2 4.7h d1 30v, 2a r fbx 143k c in 4.7f 0.1f 2.2nf 47pf c out2 10f s s downloaded from: http:/// lt8582 16 8582f applications information layout guidelines for lt8582 general layout guidelines ? to improve thermal performance, solder the exposed ground pad of the lt8582 to the ground plane, with multiple vias in and around the pad connecting to ad- ditional ground planes. ? a ground plane should be used under the switcher circuitry to prevent interplane coupling and reduce overall noise. ? high speed switching paths (see specific topology below for more information) must be kept as short as possible. ? the v c , fbx and r t components should be placed as close to the lt8582 as possible, while being as far away as practically possible from the switch node. the ground for these components should be separated from the switch current path. ? place the bypass capacitors for the v in pins (c vin ) as close as possible to the lt8582. ? place the bypass capacitors for the inductors (c pwr ) as close as possible to the inductors. ? bypass capacitors c pwr and c vin may be combined into a single bypass capacitor, c in , if the input side of the inductor can be close to the v in pin of the lt8582. boost topology specific layout guidelines ? keep length of loop (high speed switching path) gov- erning switch, diode d1, output capacitor c out1 and ground return as short as possible to minimize parasitic inductive spikes during switching. sepic topology specific layout guidelines ? keep length of loop (high speed switching path) gov- erning switch, flying capacitor c1, diode d1, output capacitor c out1 and ground return as short as possible to minimize parasitic inductive spikes during switching. inverting topology specific layout guidelines ? keep ground return path from the cathode of d2 (to chip) separated from output capacitor c out3 s ground return path (to chip) in order to minimize switching noise coupling into the output. notice the separate ground return for d2s cathode in figure 8. ? keep length of loop (high speed switching path) gov- erning switch, flying capacitor c1 (in figure 8), diode d2 and ground return as short as possible to minimize parasitic inductive spikes during switching. downloaded from: http:/// lt8582 17 8582f figure 8. suggested component placement for boost and dual inductor inv erting topologies. note the separate ground return for the r t , ss, and v c components as well as d2s cathode applications information thermal considerations overview for the lt8582 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. this can be accomplished by taking advantage of the thermal pad on the underside of the chip. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the chip and into copper planes with as much area as possible. power and thermal calculations power dissipation in the lt8582 chip comes from four primary sources: switch i 2 r loss, npn base drive loss (ac + dc) and chip bias current. the following formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents. 1 2 3 4 6 7 9 10 11 12 24 25 23 22 21 19 18 16 15 14 13 l1 s s d2 l2 l3 c1 m1 v in +C snc1 clkout2 c pwr2 c pwr1 c out1 c vin1 8582 f08 c vin2 r gate c out3 d1 gnd v out2 c out2 v out1 17 5 8 20 downloaded from: http:/// lt8582 18 8582f figure 9. suggested component placement for sepic and dual inductor i nverting topologies. note the separate ground return for the r t , ss, and v c components as well as d2s cathode applications information 1 2 3 4 6 7 9 10 11 12 24 25 23 22 21 19 18 16 15 14 13 s s d2 l3 l4 c2 snc1 clkout2 c pwr2 c pwr1 c out1 c vin1 8582 f09 c vin2 c out2 d1 c1 17 5 8 20 s s l1 l2 gnd v out2 v out1 v in +C downloaded from: http:/// lt8582 19 8582f applications information table 4 calculates the power dissipation of one channel of the lt8582 for a particular boost application (v in = 5v, v out = 12v, i out = 0.8a, f osc = 1.5mhz, v d = 0.5v, v cesat = 0.270v). from p total in table 4, die junction temperature can be calculated using the appropriate thermal resistance number and worst-case ambient temperature: t j = t a + ja ? p total where t j = die junction temperature, t a = ambient tem- perature and ja is the thermal resistance from the silicon junction to the ambient air. the published ja value is 34c/w for the 7mm 4mm 24-pin dfn package package. in practice, lower ja values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the board layout guidelines section. for instance, a ja value of ~16c/w was consistently achieved for dfn packages of the lt8582 (at v in = 5v, v out = 12v, i out = 0.8a, f osc = 1.5mhz) when board layout was optimized as per the suggestions in the board layout guidelines section. junction temperature measurement the duty cycle of clkout2 is linearly proportional to die junction temperature (t j ) near the clkout2 pin. to get an accurate reading, measure the duty cycle of the clkout signal and use the following equation to approximate the junction temperature: t j = dc clkout C 34.5% 0.3% where dc clkout is the clkout duty cycle in % and t j is the die junction temperature in c. although the absolute die temperature can deviate from the above equation by 10c, the relationship between the clkout duty cycle and change in die temperature is well defined. a 3% increase in clkout duty cycle corresponds to ~10c increase in die temperature. note that the clkout pin is only meant to drive capacitive loads up to 120pf. thermal lockout when the die temperature exceeds 165c (see operation section), a fault condition occurs and the part goes into thermal lockout. the fault condition ceases when the die temperature drops to ~160c (nominal). table 4. calculations example with v in = 5v, v out = 12v, i out = 0.8a, f osc = 1.5mhz, v d = 0.5v, v cesat = 0.27v definition of variables equation design example value dc = switch duty cycle dc = v out Cv in + v d v out + v d Cv cesat dc = 12v C 5v + 0.5v 12v + 0.5v C 0.270v dc = 61.3% i in = average input current = power conversion efficiency (typically 88% at high currents) i in = v out ?i out v in ? i in = 12v ? 0.8a 5v ? 0.88 i in = 2.18a p sw = switch i 2 r loss r sw = switch resistance (typically 95m combined swa and swb) p sw = dc ? i in 2 ? r sw p sw = 0.613 ? (2.18a) 2 ? 95m p sw = 277mw p bac = base drive loss (ac) p bac = 13ns ? i in ? v out ? f osc p bac = 13ns ? 2.18a ? 12v ? 1.5mhz p bac = 511mw p bdc = base drive loss (dc) p bdc = v in ?i in ?dc sw _ at _i in p bdc = 5v ? 2.18a ? 0.613 50 p bdc = 134mw p inp = chip bias loss p inp = 11ma ? v in p inp = 11ma ? 5v p inp = 55mw p total = 977mw note: these power calculations are for one channel of the lt8582. the power consumption of both channels should be taken into account when calculating die temperature. downloaded from: http:/// lt8582 20 8582f applications information switching frequencythere are several considerations in selecting the operat- ing frequency of the converter. the first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in rf communication prod- ucts with a 455khz if, switching above 600khz is desired. communication products with sensitivity to 1.1mhz would require to set the switching frequency to 1.5mhz or higher. also, like any other switching regulator, harmonics of much higher frequency than the switching frequency are also produced. the second consideration is the physical size of the converter. as the operating frequency goes up, the inductor and filter capacitors go down in value and size. the trade-off is efficiency, since the switching losses due to inductor ac loss, npn base drive (see thermal calcula- tions), schottky diode charge and other capacitive loss terms increase proportionally with frequency. oscillator timing resistor (r t ) the operating frequency of the lt8582 can be set by the internal free running oscillator. when the sync pin for a channel is driven low (< 0.4v), the oscillator frequency for that channel is set by a resistor from the rt pin to ground. the oscillator frequency is calculated using the following formula: f osc = 81.6 r t + 1 where f osc is in mhz and r t is in k. conversely, r t (in k) can be calculated from the desired frequency (in mhz) using: r t = 81.6 f osc C1 clock synchronization the operating frequency of each channel of the lt8582 can be set by an external source by simply providing a clock into the sync pin for that channel (r t resistor still required). the lt8582 will revert to its internal free running oscillator clock (set by the r t resistor) when the sync pin is driven below 400mv for several free running clock periods. driving the sync pin of a channel high for an extended period of time effectively stops the oscillator for that chan- nel. as a result, the switching operation for that channel of the lt8582 will stop and the clkout pin of that channel will be pulled low. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: (1) sync may not toggle outside the frequency range of 200khz to 2.5mhz. (2) the sync frequency can be higher than the free run- ning oscillator frequency (as set by the r t resistor), f osc , but should not be less than 25% below f osc . clock synchronization of additional regulators the clkout pins of the lt8582 can be used to synchro- nize additional switching regulators or other channels of lt8582s, as shown in the typical application figure on the front page. the frequency of channel 1 of the lt8582 is set by the external r t resistor. the sync pin of channel 2 of the lt8582 is driven by the clkout pin of channel 1 of the lt8582. channel 1s clkout pin has a 50% duty cycle intended for driving sync2 and is 180 out of phase for reduced input ripple or multiphase topologies. note that the rt pin of channel 2 of the lt8582 must have a resistor tied to ground. it takes a few clock cycles for the clkout signal to begin oscillating and it is preferable for all lt8582 channels to have the same internal free running frequency. therefore, in general, use the same value r t resistor for all of the synchronized lt8582s. event based sequencing the pg pin may be used to sequence other ics since it is pulled low as long as the lt8582 is enabled and the magnitude of the output voltage is below regulation (refer to the block diagram). since the pg pin is an open drain output, it can be used to pull the shdn pin of another ic low until the output of one of the channels of the lt8582 downloaded from: http:/// lt8582 21 8582f applications information is close to its regulation voltage. this method allows the pg pin to disable multiple ics. refer to figure 10 for the necessary connections. alternatively, the pg pin may be used to pull the ss pin of another switching regulator low, preventing the other regulator from switching. ? the master switch, immune from the flying capaci- tor current spike (seen only by the slave switch), can therefore sense the inductor current more accurately. ? since the slave switch can sustain large current spikes, the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements, as well as a smaller solution size. high v out charge pump topology the lt8582 can be used in a charge pump topology as shown in figure 11, multiplying the output of a boost converter. the master switch (swa) can be used to drive the boost converter, while the slave switch (swb) can be used to drive one or more charge pump stages. this topology is useful for high voltage applications including vfd bias supplies. figure 10. using the two lt8582 channels, with power supply sequencing pg1 r uvlo2 r uvlo1 set r uvlo1 and r uvlo2 such that vin1 uvlo < vin2 uvlo see configurable undervoltage lockout section for details 10k v in shdn sys shdn2 shdn1 lt8582 8582 f10 ch1master ch2 slave charge pump aided regulators designing charge pumps with the lt8582 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the ic. although the slave switch, swb, operates in phase with the master switch, swa, only the current through the master switch (swa) is sensed by the current comparator (a4 in the block diagram). this method of operation by the master/slave switches can offer the following benefits to charge pump designs: ? the slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes without falsely tripping the current comparator. in a charge pump, these spikes occur when the flying capacitors charge up. since this current spike flows through swb, it does not affect the operation of the current comparator (a4 in the block diagram). ss gnd sync swb swa lt8582 chx 8582 f11 pgrt v in shdn clkout v c fbx gate v in 9v to 16v 100k 576k 80.6k 21k 22h 383k 4.7f 2.2f 2.2f 2.2f 2.2f 2.2f 1.5nf 47pf 2.2f 8.06k 2.2f v out1 100v80ma v out2 66v120ma figure 11. high v out charge pump topology downloaded from: http:/// lt8582 22 8582f applications information single inductor inverting topology if there is a need to use just one inductor to generate a negative output voltage whose magnitude is greater than v in , the single inductor inverting topology (shown in figure 12) can be used. since the master and slave switches are isolated by a schottky diode, the current spike through c1 will flow only through the slave switch, preventing the current comparator, (a4 in the block diagram) from false tripping. output disconnect is inherently built into the single inductor topology. hot-plug high inrush currents associated with hot-plugging v in can largely be rejected with the use of an external pmos. a simple hot-plug controller can be designed by connecting an external pmos in series with v in , with the gate of the pmos being driven by the gate pin of the lt8582. the gate pin pull-down current is linearly proportional to the ss voltage. since the ss charge up time is relatively slow, the gate pin pull-down current will increase gradually, thereby turning on the external pmos slowly. controlled in this manner, the pmos acts as an input current limiter when v in hot-plugs or ramps up sharply. likewise, when the pmos is connected in series with the output, inrush current into the output capacitor can be limited during a hot-plug event. to illustrate this, the circuit in figure 5 was reconfigured by adding a large 1500f capacitor to the output. an 18 resistive load was used and c ss was increased to 10f. figure 13 shows the results of hot-plugging this reconfigured circuit. notice how the inductor current is well behaved. figure 12. single inductor inverting topology figure 13. v in hot-plug control. inrush current is well controlled ss gnd sync swb c1 swa lt8582 chx 8582 f12 pgrt v in shdn clkout v c fbx gate v out < 0v and |v out | > v in v in 100k r t r c l1 d1 d3 d2 r fbx c in c ss c c c f c out v in 5v/div v out1 10v/div i l1 2a/div 2s/div ss1 1v/div 8582 f13 downloaded from: http:/// lt8582 23 8582f appendix independent channelseither channel may be used independently of the other channel. to disable one channel, drive shdn of that channel low. activating or deactivating one channel will not alter the functionality of the other channel. setting the output voltage the output voltage is set by connecting a resistor (r fbx ) from v out to the fbx pin. r fbx is determined by using the following equation: r fbx = |v out Cv fbx | 83.3a where v fbx is 1.204v (typical) for noninverting topologies (i.e. boost and sepic regulators) and 7mv (typical) for inverting topologies (see the electrical characteristics). power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npns (q1 and q2 in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = (t p Cminofftime) t p ? 100% where t p is the clock period and minofftime (found in the electrical characteristics) is typically 45ns. conversely, the power npns (q1 and q2 in the block diagram) cannot remain off for 100% of each clock cycle and will turn on for a minimum on time (minontime) when in regulation. this minontime governs the minimum al- lowable duty cycle given by: dc min = minontime t p ? 100% where t p is the clock period and minontime (found in the electrical characteristics) is typically 55ns.the application should be designed such that the operating duty cycle is between dc min and dc max . duty cycle equations for several common topologies are given below where v d is the diode forward voltage drop and v cesat is the collector to emitter saturation voltage of the switch. v cesat , with swa and swb tied together, is typically 270mv when the combined switch current (i swa + i swb ) is 2.75a. for the boost topology (see figure 5): dc boost ? v out Cv in + v d v out + v d Cv cesat for the sepic or dual inductor inverting topology (see figure 6 and figure 7): dc sepic _& _ invert ? |v out | + v d v in + |v out | + v d Cv cesat for the single inductor inverting topology (see figure 12): dc si_ invert ? |v out |Cv in + v cesat + 3?v d |v out | + 3?v d the lt8582 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. inductor selection general guidelines the high frequency operation of the lt8582 allows for the use of small surface mount inductors. for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper- wire resistance) to reduce i 2 r losses and must be able to handle the peak inductor current without saturating. note that in some applications, the current handling require- ments of the inductor can be lower, such as in the sepic topology where each inductor only carries one half of the total switch current. multilayer chip inductors usually do not have enough core volume to support peak inductor currents in the 2a to 6a range. to minimize radiated noise, downloaded from: http:/// lt8582 24 8582f appendix use a toroidal or shielded inductor. see table 5 for a list of inductor manufacturers. table 5. inductor manufacturers coilcraft msd7342 xal6060 series www.coilcraft.com vishay ihlp-2020bz-01 ihlp-2525cz-01series www.vishay.com wrth we-pd we-ddwe-tdc series www.we-online.com cooper bussman octa-pac plus drq-125drq-74 series www.cooperbussmann.com sumida cdr6d28mn cdr7d28mnseries www.sumida.com taiyo yuden nr series www.t-yuden.com tdk vlf, slf, rlf series www.tdk.com minimum inductance although there can be a trade-off with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are three conditions that limit the minimum inductance: (1) providing adequate load current, (2) avoiding subharmonic oscillation and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. adequate load current small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. in order to provide adequate load current, l should be at least: l boost # dc t (v in C v cesat ) 2 t f osc t i pk C v out t i out v in t m ? ? a 1 ? o boost topology or l dual # dc t (v in Cv cesat ) 2 t f osc t i pk C |v out | t i out v in t m i out ? ? a 1 ? o sepic or inverting topologies where l boost = l1 for boost topologies (see figure 5) l dual = l1 = l2 for coupled dual inductor topologies (see figures 6 and 7) l dual = l1 || l2 for uncoupled dual inductor topologies (see figures 6 and 7) dc = switch duty cycle (see power switch duty cycle section in appendix) i pk = maximum peak switch current; should not exceed 3a for a combined swa + swb current, or 1.7a if only swa is being used. = power conversion efficiency (typically 88% for boost and 82% for dual inductor topologies at high currents) f osc = switching frequency i out = maximum load current negative values of l boost or l dual indicate that the output load current i out exceeds the switch current limit capability of the lt8582. avoiding subharmonic oscillations subharmonic oscillations can occur when the duty cycle is greater than 50%. the lt8582s internal slope compensa- tion circuit will avoid this, provided that the inductance exceeds a certain minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l min (v in Cv cesat )?(2?dcC1) 1.7a ? f osc ?(1Cdc) where l min = l1 for boost topologies (see figure 5) l min = l1 = l2 for coupled dual inductor topologies (see figures 6 and 7) l min = l1 || l2 for uncoupled dual inductor topologies (see figures 6 and 7) downloaded from: http:/// lt8582 25 8582f appendix maximum inductanceexcessive inductance can reduce current ripple to levels that are difficult for the current comparator (a4 in the block diagram) to easily distinguish the peak current. this causes duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in Cv cesat 180ma ? dc f osc where l max = l1 for boost topologies (see figure 5) l max = l1 = l2 for coupled dual inductor topologies (see figures 6 and 7)l max = l1 || l2 for uncoupled dual inductor topologies (see figures 6 and 7) inductor current ratinginductors must have a rating greater than their peak operating current to prevent saturation, which results in efficiency losses. the maximum inductor current (con- sidering start-up, transient, and steady-state conditions) is given by: i l _ peak = i lim + v in ?t min _ prop l where i l_peak = peak of inductor current in l1 for boost topology, or peak of the sum of inductor currents in l1 and l2 for dual inductor topologies. i lim = for hard saturation inductors, 5.4a when swa and swb are tied together, or 3a when only swa is being used. for soft saturation inductors, 3.3a when swa and swb are tied together, or 1.8a when only swa is being used. t min_prop = 55ns (propagation delay through the current feedback loop) note that these equations offer conservative results for the required inductor current ratings. the current ratings could be lower for applications with light loads and small transients if the ss capacitor is sized appropriately to limit inductor currents at start-up. diode selection schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the lt8582. choose a schottky diode with low parasitic capacitance to reduce reverse current spikes through the power switch of the lt8582. the diodes inc. pd3s230h diode is a very good choice with a 30v reverse voltage rating and an average forward current of 2a. output capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple volt- age. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r or x7r types are preferred, as these retain their capacitance over wide voltage and temperature ranges. a 10f to 22f output capacitor is sufficient for most applications, but systems with very low output currents may need only 2.2f to 10f. always use a capacitor with a sufficient voltage rating. many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. tantalum polymer or os-con capacitors can be used, but it is likely that these capacitors will occupy more board area than ceramics and will have a higher esr with greater output ripple. input capacitor selection ceramic capacitors make a good choice for the input by- pass capacitor and should be placed as close as possible to the v in pin of the chip as well as to the inductor con- nected to the input of the power path. if it is not possible to optimally place a single input capacitor, then use two separate capacitorsuse one at the v in pin of the chip (see the equation for c vin in table 1, table 2 and table 3) downloaded from: http:/// lt8582 26 8582f appendix and one at the input to the power path (see the equation for c pwr in table 1, table 2 and table 3). a 4.7f to 20f input capacitor is sufficient for most applications. table 6 shows a list of several ceramic capacitor manufac- turers. consult the manufacturers for detailed information on their entire selection of ceramic parts. table 6. ceramic capacitor manufacturers tdk www.tdk.com murata www.murata.com taiyo yuden www.t-yuden.com kemet www.kemet.com pmos selection an external pmos, controlled by the lt8582s gate pin, can be used to facilitate input or output disconnect. the gate pin turns on the pmos gradually during start-up (see soft-start of external pmos in the operation section) and turns the pmos off when the lt8582 is in shutdown or in fault. the use of the external pmos, controlled by the gate pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. in a conventional boost regulator, the inductor, schottky diode and power switches are susceptible to damage in the event of an output short. using an external pmos in the boost regulators power path (path from v in to v out ) controlled by the gate pin, will serve to disconnect the input from the output when the output has a short. this helps to save the chip and the other components in the power path from damage. ensure that both the diode and the inductor can survive low duty cycle current pulses of 5 to 6 times their steady state levels. the pmos chosen must be capable of handling the maxi- mum input or output current depending on whether it is used at the input or the output (see figure 5). ensure that the pmos is biased with enough source to gate voltage (v sg ) to enhance the device into the triode mode of operation. the higher the v sg voltage that biases the pmos into triode, the lower the r dson of the pmos, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application. the following equations show the relation- ship between r gate (see block diagram) and the desired v sg that the pmos is biased with, where v s is the pmos source voltage: v gs = v s r gate r gate + 2k if v gate < 2v 1m a t r gate if v gate 2v when using a pmos, it is advisable to configure the specific application for undervoltage lockout (see the operations section). the goal is to have v in get to a certain minimum voltage where the pmos has sufficient v sg . figure 5 shows the pmos connected in series with the output to act as an output disconnect during a fault con- dition. using a pmos with a high v t (~2v) can help to reduce extraneous current spikes during hot-plug. the resistor divider from v in to the shdn pin sets uvlo at 4v for this application. connecting the pmos in series with the output offers cer- tain advantages over connecting it in series with the input: ? since the load current is always less than the input current for a boost converter, the current rating of the pmos will be reduced. ? a pmos in series with the output can be biased with a higher overdrive voltage than a pmos used in series with the input, since v out > v in . this higher overdrive results in a lower r dson rating for the pmos, thereby improving the efficiency of the regulator. in contrast, an input connected pmos works as a simple hot-plug controller (covered in more detail in the hot-plug section). the input connected pmos also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the lt8582 with other compatible chips. downloaded from: http:/// lt8582 27 8582f appendix table 7 shows a list of several discrete pmos manufactur- ers. consult the manufacturers for detailed information on their entire selection of pmoss. table 7. discrete pmos manufacturers vishay www.vishay.com on semiconductor www.onsemi.com fairchild semiconductor www.fairchildsemi.com diodes incorporated www.diodes.com compensation C adjustment to compensate the feedback loop of the lt8582, a series resistor capacitor network in parallel with an optional single capacitor should be connected from the v c pin to gnd. for most applications, choose a series capacitor in the range of 1nf to 10nf with 2.2nf being a good start- ing value. the optional parallel capacitor should range in value from 22pf to 220pf with 47pf being a good starting value. the compensation resistor, r c , is usually in the range of 5k to 50k with 10k being a good starting value. a good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor r c . with the series and parallel capacitors at 4.7nf and 47pf respectively, adjust the potentiometer while observ- ing the transient response and the optimum value for r c can be found. figures 14a to figure 14c illustrate this process for the circuit of figure 17 with a load current stepped between 300ma and 800ma. figure 14a shows the transient response with r c equal to 1k. the phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. in figure 14b, the value of r c is increased to 3.15k, which results in a more damped response. figure 14c shows the results when r c is increased further to 6.49k. the transient response is nicely damped and the compensation procedure is complete. compensation C theorylike all other current mode switching regulators, the lt8582 needs to be compensated for stable and efficient operation. two feedback loops are used in the lt8582: a fast current loop which does not require compensation and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 15 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the chip, inductor and diode have been replaced by a combination of the equivalent transcon- ductance amplifier g mp and the current controlled current source (which converts i vin to ( v in /v out ) ? i vin ). g mp acts as a current source where the peak input current, i vin , is proportional to the v c voltage. is the efficiency of the switching regulator and is typically about 88% at higher currents. figure 14a. transient response shows excessive ringing figure 14b. transient response is better figure 14c. transient response is well damped v out1 ac-coupled 500mv/div i load 400ma/div i l1 1a/div 100s/div 8582 f14a v out ac-coupled 500mv/div i load 400ma/div i l 1a/div 100s/div 8582 f14b v out ac-coupled 500mv/div i load 400ma/div i l 1a/div 100s/div 8582 f14c downloaded from: http:/// lt8582 28 8582f appendix note that the maximum output currents of g mp and g ma are finite. the output current of the g mp stage is limited by the minimum switch current limit (see the electrical specifications) and the output of the g ma stage is nominally limited to about 12a.from figure 15, the dc gain, poles and zeros can be calculated as follows: dc gain: a dc = (g ma ?r o )?g mp ? ? v in v out ? r l 2 ?? ? ?? ? ? 0.5r 2 r 1 + 0.5r 2 output pole: p 1 = 2 2? ?r l + c out error amp pole: p2 = 1 2? ?(r o + r c ) c c error amp zero: z1 = 1 2? ?r c ?c c esr zero: z2 = 1 2? ?r esr ?c out rhp zero: z3 = v in 2 ?r l 2? ?v out 2 ?l high frequency pole: p3 f s 3 phase lead zero: z4 = 1 2? ?r1?c pl phase lead pole: p4 = 1 2? 0.5 ? r 1 ?r 2 r 1 + 0.5r 2 ?c pl error amp filter pole: p5 = 1 2? ? r c ?r o r c + r o ?c f ,c f < c c 10 figure 15. boost converter equivalent model 8582 f15 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductor error amplifier inside the chip g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out /i loadmax r o : output resistance of gma r1, r2: output voltage feedback resistor divider r esr : output capacitor esr m : converter efficiency (~88% at higher currrents) i vin c pl c f C + C + 1.204v reference c c r c r o r2 r1 v out r l r2 fbx g ma g mp m t 7 in v out t * vin r esr c out downloaded from: http:/// lt8582 29 8582f the current mode zero (z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. using the circuit in figure 17 as an example, table 8 shows the parameters used to generate the bode plot shown in figure 16. table 8. bode plot parameters parameter value units comment r l 20 application specific c out 22 f application specific r esr 1 m application specific r o 305 k not adjustable c c 4700 pf adjustable c f 47 pf optional/adjustable c pl 0 pf optional/adjustable r c 6.49 k adjustable r1 130 k adjustable r2 14.5 k not adjustable v ref 1.204 v not adjustable v out 12 v application specific v in 5 v application specific g ma 270 mho not adjustable g mp 15.1 mho not adjustable l 4.7 h application specific f osc 1.5 mhz adjustable from figure 16, the phase is C130 when the gain reaches 0db, giving a phase margin of 50. the crossover frequency is 5khz, which is many times lower than the frequency of the rhp zero z3, thus providing for adequate phase margin. appendix figure 16. bode plot for example boost converter figure 17. 5v to 12v boost converter frequency (hz) 10 C20 gain (db) phase (deg) 0 100 8060 40 120 1k 10k 8582 f16 20 100 100k 1m 140 C360 C315 C90C135 C180 C225 C45 C270 0 phase 50 at5khz gain ss gnd sync swb swa lt8582 chx 8582 f17 pgrt v in shdn clkout vc fbx gate v out 12v v in 5v 100k 215k r t 53.6k 6.49k l1 4.7h d1 130k c in 4.7f 0.1f 4.7nf 47pf c out 22f downloaded from: http:/// lt8582 30 8582f typical applications 1.5mhz, 5v to 12v boost and inverting converter can survive output sh orts efficiency and power loss (load between 12v and C12v outputs) output short from 12v output to ground transient response with 0.15a to 0.45a to 0.15a output load step between rails load current (a) 0 20 efficiency (%) power loss (w) 30 8070 60 50 90 0.2 0.3 0.6 8582 ta02b 40 0.1 0.4 0.5 100 0 0.4 2.42.0 1.6 1.2 2.8 0.8 3.2 v out1 5v/div clkout1 5v/div gate 5v/div i l1 5a/div 20s/div 8582 ta02c v out1 500mv/div ac-coupled v out2 500mv/div ac-coupled i l1 1a/div i l2 + i l3 1a/div 100s/div 8582 ta02d swb2 swa2 swb1 swa1 lt8582 8582 ta02a pg1sync1 clkout1 clkout2 215k100k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 12v0.8a* v out2 C12v550ma* c1 2.2f v in 5v 0.1f 0.1f 4.7nf 47pf47pf 14.7k 6.49k 100k 215k 143k l2 4.7h s l1 4.7h 2.2nf 6.04k c out3 10f c out2 10f 130k 53.6k53.6k c in2 4.7f c in1 , c in2 : 4.7f, 16v, x7r, 1206 c out1 , c out2 , c out3 : 10f, 25v, x7r, 1206 c1: 2.2f, 25v, x7r, 1206 d1, d2: diodes inc. pd3s230h l1: coilcraft xal6060-472ml l2, l3: coilcraft msd7342-472 m1: fairchild fdmc510p *max total output power: 14.4w c out1 10f d1 m1 c in1 4.7f d2 l3 4.7h s downloaded from: http:/// lt8582 31 8582f typical applications vfd (vacuum fluorescent display) and filament power supply switches at 1mhz efficiency and power loss (v in = 12v with load on 10.5v output) efficiency and power loss (v in = 12v with load on 100v output) output power (w) 0 50 efficiency (%) power loss (w) 8070 4 6 8582 ta03b 60 2 8 10 90 0.4 1.61.2 0.8 2.0 load current (a) 0 20 efficiency (%) power loss (w) 8070 60 50 0.4 0.6 8582 ta03c 4030 0.2 0.8 1 100 90 0 0.2 1.2 1.40.8 1.0 0.4 0.6 1.6 swb2 swa2 swb1 swa1 lt8582 8582 ta03a pg1sync1 clkout1 clkout2 576k100k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out3 10.5v0.85a c7 2.2f v in 9v to 16v 2.2f2.2f 1.5nf 47pf47pf 11.8k 21k 100k 576k 113k l2 10h s l1 22h 1.5nf 8.06k** d7** c810f 2 c22.2f 383k 80.6k80.6k c in2 4.7f c in1 , c in2 : 4.7f, 25v, x7r, 1206 c1 to c6: 2.2f, 50v, x7r, 1206 c7: 2.2f, 25v, x7r, 0805 c8: 10f, 25v, x7r, 1210 d1 to d6: central semi cmmsh2-40 d7: central semi cmhz5240b d8: central semi ctlsh5-40m833 d9: central semi ctlsh2-40m832 l1: wrth 744771122 l2, l3: wrth 744870100 m1: vishay si7611dn *channel 1 max output power 8w **optional for output short protection c12.2f d1 d2 d3 d5 d6d4 d8** m1** c32.2f c42.2f c52.2f v out2 66v120ma* v out1 100v80ma* c62.2f c in1 4.7f d9 l310h s downloaded from: http:/// lt8582 32 8582f typical applications tracking 15v supplies from a 2.7v to 5.5v input 15v and C15v outputs vs load current (v in = 3.6v, load on 15v output) 15v and C15v outputs vs load current (v in = 3.6v, load between 15v and C15v outputs) 15v and C15v outputs vs load current (v in = 3.6v, load on C15v output) efficiency and power loss (v in = 3.6v with load between 15v and C15v outputs) load current (a) 0 20 efficiency (%) power loss (w) 8070 60 50 0.1 0.15 8582 ta04b 4030 0.05 0.2 0.25 0.3 0.35 0.4 100 90 0 0.4 2.4 2.81.6 2.0 0.8 1.2 3.2 load current (a) 0 14.90 magnitude v out (v) 15.2015.15 15.10 15.05 0.1 0.15 8582 ta04c 15.1014.95 0.05 0.2 0.25 0.3 0.35 0.45 0.4 15.3015.25 15v C15v load current (a) 0 14.90 magnitude v out (v) 15.2015.15 15.10 15.05 0.1 0.15 8582 ta04d 15.0014.95 0.05 0.2 0.25 0.3 0.35 0.4 15.3015.25 15v C15v load current (a) 0 14.90 magnitude v out (v) 15.2015.15 15.10 15.05 0.1 0.15 8582 ta04e 15.1014.95 0.05 0.2 0.25 0.3 0.35 0.4 15.3015.25 15v C15v swb2 swa2 swb1 swa1 lt8582 8582 ta04a pg1sync1 clkout1 clkout2 100k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 15v0.3a(v in = 2.7v) 0.42a(v in = 3.6v) 0.56a(v in = 4.5v) 0.69a(v in = 5.5v) v out2 C15v0.27a(v in = 2.7v) 0.37a(v in = 3.6v) 0.46a(v in = 4.5v) 0.54a(v in = 5.5v) c1 4.7f v in 2.7v to 5.5v 0.1f 0.1f 6.8nf 100pf100pf 6.65k 6.65k 53.6k l2 15h s l1 10h 6.8nf 6.04k fbx2 c out2 10f2 c out1 10f2 49.9k 107k107k c in2 10f c in1 , c in2 : 10f, 16v, x7r, 1206 c out1 , c out2 : 10f, 25v, x7r, 1210 c1: 4.7f, 50v, x7r, 1206 d1, d2: diodes inc. pd3s230h l1: coilcraft xal6060-103me l2, l3: coilcraft msd1260-153 d1 c in1 10f d2 l3 15h s downloaded from: http:/// lt8582 33 8582f typical applications supercap backup power input removed, holdup for ~110s with 500ma load charging supercaps system level diagram gate sepic 8582 ta05b v out1 supercaps v in1 v in boost v out2 v out v in2 swb2 swa2 swb1 swa1 lt8582 8582 ta05a pg1sync1 clkout1 clkout2 73.2k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 10v v out v in (v in > 11.4v) 11v (v in < 11.4v) v in 12v 5% v out1 0.47f0.47f 1nf 100pf100pf 12.7k 15.4k 100k 100k 105k l3 2.2h l1 5h l25h 3.3nf c s4 60f 1.2k1/4w 130k m1 c out3 22f2 c out2 10f 11k 80.6k 80.6k c in2 4.7f c in1 , c in2 : 4.7f, 16v, x7r, 1206 c out1 : 4.7f, 25v, x7r, 1206 c out2 : 10f, 25v, x7r, 1210 c out3 : 22f, 16v, x7r, 1210 c1: 2.2f, 25v, x7r, 0805 c s1 to c s4 : 60f, 2.5v, cooper hb1840-2r5606-r d1, d2: central semi ctlsh5-40m833l1, l2: cooper ctx5-1a l3: cooper hcm0703-2r2 m1: vishay si7123dn c1 2.2f d1 c in1 4.7f c out1 4.7f d2 s s c s3 60f 1.2k1/4w c s2 60f 1.2k1/4w c s1 60f 1.2k1/4w 6.04k v out v in 5v/div v out1 5v/div i l3 2a/div i l1 + i l2 2a/div 25s/div 8582 ta05c v out 11v 5v/div v out1 5v/div i l3 2a/div i l1 + i l2 2a/div 25s/div 8582 ta05d downloaded from: http:/// lt8582 34 8582f typical applications 12v and 5v sequenced outputs from a 3v to 19v input* efficiency and power loss (v in = 12v with load on 5v output) efficiency and power loss (v in = 12v with load on 12v output) cycle-to-cycle (5v output) start-up waveforms (v in = 12v) load current (a) 0 0 efficiency (%) power loss (w) 2010 7060 50 40 80 0.4 0.6 0.8 1.6 8582 ta06e 30 0.2 1 1.2 1.4 100 90 0 0.25 1.501.25 1.00 0.75 1.75 0.50 2.502.25 2.00 load current (a) 0 20 efficiency (%) power loss (w) 30 8070 60 50 90 0.4 0.6 1 8582 ta06d 40 0.2 0.8 100 0 0.3 1.81.5 1.2 0.9 2.1 0.6 2.4 v out2 50mv/div ac-coupled clkout2 2v/div swa2, swb2 10v/div i l3 + i l4 1a/div 500ns/div 8582 ta06c v out2 2v/div v out1 5v/div i l1 + i l2 2a/div i l3 + i l4 2a/div 2ms/div 8582 ta06b swb2 swa2 swb1 swa1 lt8582 8582 ta06a pg1sync1 clkout1 clkout2 115k 10k shdn sys m1 m2 sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 12v0.3a (v in = 3v) 0.5a (v in = 5v) 1a (v in = 12v) v out2 5v0.7a (v in = 3v) 1a (v in = 5v) 1.45a (v in = 12v) v in 3v to 19v 0.1f 0.1f 1.5nf 47pf47pf 14.7k 20k 100k 45.3k l3 6.8h s l1 8.2h l28.2h 1.5nf 130k c out2 22f2 c out1 10f2 107k107k c in2 10f c in1 , c in2 : 10f, 25v, x7r, 1210 c out1 : 10f, 25v, x7r, 1210 c out2 : 22f, 16v, x7r, 1210 c 1 ,c 2 : 2.2f, 25v, x7r, 0805 d1, d2: central semi ctlsh2-40m832l1, l2: cooper drq125-8r2 l3, l4: cooper drq125-6r8 m1, m2: 2n7002 *for system level diagram,see figure 10 c1 2.2f d1 c in1 10f d2 s s 10k l46.8h s c2 2.2f downloaded from: http:/// lt8582 35 8582f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. dkd package 24-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1864 rev ?) note: 1. drawing proposed to be made variation of version (wxxx) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) bottom viewexposed pad r = 0.115 typ 0.25 p 0.05 1 12 13 24 5.50 ref 6.43 p 0.10 2.64 p 0.10 4.00 p 0.10 0.75 p 0.05 0.00 C 0.05 0.200 ref 7.00 p 0.10 (dkd24) qfn 0210 rev ? 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer 6.43 p 0.05 2.64 p 0.05 0.70 p 0.05 0.50 bsc 5.50 ref 3.10 p 0.05 4.50 p 0.05 0.40 p 0.10 0.25 p 0.05 package outline r = 0.05 typ package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:/// lt8582 36 8582f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0112 printed in usa swb2 swa2 swb1 swa1 lt8582 8582 ta07a pg1sync1 clkout1 clkout2 100k sync2pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 5v0.7a (v in = 3v) 1.4a (v in = 9v) 1.5a (v in = 16v) v out2 C5v0.7a (v in = 3v) 1.4a (v in = 9v) 1.5a (v in = 16v) v in 3v to 19v 0.1f 0.1f 2.2nf 47pf47pf 18.7k 11.8k 100k 60.4k l3 4.7h s l1 4.7h l24.7h 2.2nf 45.3k c out2 22f2 c out1 22f2 115k115k c in2 22f c in1 , c in2 : 22f, 25v, x7r, 1210 c out1 , c out2 : 22f, 16v, x7r, 1210 c 1 , c 2 : 2.2f, 50v, x7r, 1206 d1, d2: vishay mss2p3 l1, l2: wrth we tdc 74489440047 l3, l4: wrth we tdc 74489440047 c1 2.2f d1 c in1 22f d2 s s l4 4.7h s c2 2.2f related parts typical application 700khz sepic and inverting converter generates 5v outputs from a 3v to 19v input efficiency and power loss (v in = 12v with load between 5v and C5v outputs) part number description comments lt3581 3.3a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 22v, v out(max) = 42v, i q = 1.9ma, i sd = < 1a, 4mm 3mm dfn-14, msop-16e lt3579 6a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 16v, v out(max) = 42v, i q = 1.9ma, i sd = < 1a, 4mm 5mm qfn-20, tssop-20 lt3580 2a (i sw ), 42v, 2.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 32v, v out(max) = 42v, i q = 1ma, i sd = < 1a, 3mm 3mm dfn-8, msop-8e lt3471 dual output 1.3a (i sw ), 1.2mhz, high efficiency step-up dc/dc converter v in = 2.4v to 16v, v out(max) = 40v, i q = 2.5ma, i sd < 1a, 3mm 3mm dfn-10 package lt3479 3a (i sw ), 40v, 3.5mhz, high efficiency step-up dc/dc converter v in : 2.5v to 24v, v out(max) = 40v, i q = 5ma, i sd = < 1a, 4mm 3mm dfn-14, tssop-16e lt3477 40v, 3a, full featured dc/dc converter v in = 2.5v to 25v, v out(max) = 40v, i q = 5ma, i sd < 1a, qfn, tssop-20e packages lt1946/lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz, high efficiency step-up dc/dc converter v in = 2.6v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1a, ms8e package lt1935 2a (i sw ), 40v, 1.2mhz, high efficiency step-up dc/dc converter v in = 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot? package lt1310 2a (i sw ), 40v, 1.2mhz, high efficiency step-up dc/dc converter v in = 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot package lt3436 3a (i sw ), 800khz, 34v step-up dc/dc converter v in = 3v to 25v, v out(max) = 34v, i q = 0.9ma, i sd < 6a, tssop-16e package load current (a) 0 2010 0 efficiency (%) power loss (w) 30 8070 60 50 90 1 0.6 0.8 1.2 1.6 8582 ta07b 40 0.2 0.4 1.4 0 1.00.5 3.53.0 2.5 2.0 4.0 1.5 4.5 downloaded from: http:/// |
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